This invention relates, generally, to a process for fabricating semiconduction devices and, more particularly, to processes for fabricating EEPROM devices.
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only-memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. The floating-gate electrode overlies a channel region residing between source and drain regions in a semiconductor substrate. The floating-gate electrode together with the source and drain regions forms an enhancement transistor. By storing electrical charge on the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively high value. Correspondingly, when charge is removed from the floating-gate electrode, the threshold voltage of the enhancement transistor is brought to a relatively low value. The threshold level of the enhancement transistor determines the current flow through the transistor when the transistor is turned on by the application of appropriate voltages to the gate and drain. When the threshold voltage is high, no current will flow through the transistor, which is defined as a logic 0 state. Correspondingly, when the threshold voltage is low, current will flow through the transistor, which is defined as a logic 1 state.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. Silicon nitride in combination with silicon dioxide is known to provide satisfactory dielectric separation between the control-gate electrode and the channel region of the enhancement transistor, while possessing electrical characteristics sufficient to store electrical charge. During programming, electrical charge is transferred from the substrate to the silicon nitride layer located in an oxide-nitride-oxide (ONO) layer.
Non-volatile memory designers have taken advantage of the ability of silicon nitride to store charge in localized regions and have designed memory circuits that utilize two regions of stored charge within the ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two-bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
These devices require pocket regions near the source and drain regions on either side of the channel. Electrons are sourced from the pocket regions and injected into the nitride layer. As devices are scaled to smaller dimensions, it becomes more difficult to form the pocket regions at precise locations in the channel region. While the recent advances in EEPROM technology have enabled memory designers to double the memory capacity of EEPROM arrays using two-bit data storage, numerous challenges exist in the fabrication of material layers within these devices. In particular, the pocket regions must be carefully fabricated to avoid excessive overlap with the source and drain regions. Accordingly, advances in fabrication technology are necessary to insure proper function two-bit EEPROM devices as device dimensions are scaled to smaller values.
A process for fabricating an EEPROM device advantageously enables the formation of pocket implant regions in the EEPROM device by doping the substrate at an angle of instant normal to the substrate surface. The pocket implant regions are formed by penetrating dopants through a portion of a dielectric layer exposed by an overlying resist pattern. The pocket implant regions are formed in semiconductor substrate immediately below the exposed portions of the dielectric layer. By forming the pocket regions with a doping process carried out at normal incidence to the substrate surface, precisely formed pocket regions can be obtained.
In one form, a process of the invention includes providing a semiconductor substrate having a principal surface and forming a pattern composite layer having a first edge surface. The pattern composite layer includes a dielectric layer overlying the principal surface and a resist layer overlying the dielectric layer. The resist layer is processed to form a second edge surface laterally displaced from the first edge surface. The processing of the resist layer exposes an upper surface of the dielectric layer, which separates the first edge surface from the second edge surface. A process is then carried out to penetrate the upper surface of the dielectric layer with dopants to form a doped region in the semiconductor substrate.